1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly relates to a semiconductor device including a plurality of core chips and an interface chip that controls the core chips and to a manufacturing method thereof.
2. Description of the Related Art
A memory capacity that is required in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) are increasing every year. To satisfy this requirement by increasing a memory capacity of each memory chip prevents to secure a yield rate because it requires finer processing than so far. Therefore, in recent years, a memory device that is called a multi-chip package where plural memory chips are laminated is suggested to satisfy the required memory capacity. However, since the memory chip used in the multi-chip package is a common memory chip capable of operating even though the memory chip is a single chip, a so-called front end unit that performs a function of an interface with an external device is included in each memory chip. For this reason, it is difficult to greatly increase a memory capacity for each chip.
In addition, a circuit that constitutes the front end unit is manufactured at the same time as a back end unit including a memory core, regardless of the circuit being a circuit of a logic system. Therefore there have been a further problem that it is difficult to speed up the front end unit.
As a method to resolve the above problem, a method that detaches the front end unit from each memory chips and integrate them in one interface chip and laminates these chips, thereby constituting one semiconductor memory device, is suggested. According to this method, with respect to memory chips (Hereafter, a memory chip whose front end unit was detached is called ‘a core chip’), it becomes possible to increase a memory capacity for each chip because an occupied area assignable for the memory core increases. Meanwhile, with respect to an interface chip that is integrated with the front end unit, it becomes possible to form its circuit with a high-speed transistor because the interface chip can be manufactured using a process different from that of the memory core. In addition, since the plural core chips can be allocated to one interface chip, it becomes possible to provide a semiconductor memory device that has a large memory capacity and a high operation speed as a whole.
The core chips and the interface chip are connected to each other with a through silicon via that is provided in a via hole that penetrates substrates of the core chips. Japanese Patent Application Laid-open No. 2000-150415 discloses a method of forming a via hole on a semiconductor substrate. With this method, it is possible to form a via hole having a side surface of a vertical shape (a side surface not having a bowing shape) on a semiconductor substrate. As disclosed in Japanese Patent Application Laid-open No. 2000-150415, conventionally, the side surface of the via hole is made to have a vertical shape, so that the via hole having a side surface of a bowing shape has never been manufactured.
However, in the semiconductor device including a plurality of core chips and an interface chip, when a side surface of a via hole in which a through silicon via is embedded is perpendicular to a surface of a substrate, there is a problem that the through silicon via falls out of the substrate particularly in an assembly process. That is, because the through silicon via is made of a conductive material such as copper (Cu) and tungsten (W), its adhesion to the semiconductor substrate is low. Furthermore, at the time of a solder connection in the assembly process, a load of several to several tens of newtons is applied on the through silicon via. For these reasons, the through silicon via sometimes falls out of the substrate, and an improvement for this problem has been required.